The prior IBM System/360 Model 67-2 multiprocessor system can select any of its plural processors to handle an I/O interrupt, and the I/O device sending the interrupt signal need not have been started by the processor selected to handle its I/O interrupt signal.
The System/360 M67-2 multiprocessing system could contain from two to four CPU's and one or two 2946 channel controller units (CCU); each CCU is connected to up to seven I/O channels. Each CCU controls the I/O selection of its connected channels by any CPU issuing a Start I/O (SIO) instruction. The CCU receives each I/O interrupt from its channels, and the CCU selects any available CPU for handling each received I/O interrupt. The CPU selected to handle an I/O interrupt may be different from the CPU which issued the SIO. This is described in the IBM Manual having Form No. Y27-2118-0 which was published in 1967.
In the System/360 M67-2 MP, any I/O interrupted channel sent a channel interrupt (CI) signal to the CCU. The CI signal was received by the "Interrupt Masking and Interrupt Priority Logic" in the CCU. When one or more channel interrupt signals was received by the CCU, the CI's were filtered by a mask gate matrix, one mask gate for each channel per CPU. The mask gates are enabled/disabled by mask bits in a control register 4 in each CPU. The CI signals to enabled mask gates are passed to a respective priority circuit for each CPU to permit the simultaneous selection of one CI per CPU. The priority sequence is channels 1-6, 0. When each priority circuit outputs a CI request, it is sent to the respective CPU connected to the priority circuit output. The same CI is normally broadcast to all CPU's. Since up to four CPU's could be configured in a M67-2 MP, a CI request would be broadcast to all (up to four) CPU's simultaneously.
Each M67-2 MP CPU in an interruptable condition normally responds to a CI request with an "Interrupt Response CPUX" signal back to the requesting CCU indicating that the responding CPU can handle the interrupt. (A CPU is interruptable when it is in a wait state or has reached an interruptable point during execution.) The CCU then selected one of the responding CPU's to handle the interrupt. The CCU made the CPU selection by means of its CPU On-line priority logic which gives priority among plural responding CPU's to the lowest numbered CPU, i.e., CPU1 has highest priority and CPU.varies.has lowest priority. The On-line priority logic outputs the identifier (ID) of the selected CPU.
The CCU then sends the selected CPU interrupt response signal and the selected CPU ID signal to interrupt response controls in the CCU. They respond by sending to the selected CPU the channel address of the interrupting channel and the unit address of the interrupting device received from the channel. The selected CPU can then take the interrupt by posting the received channel and device addresses, and other received information, into its channel status word (CSW) in main storage and swapping program status words (PSWs).
If all channels are masked on, only one CI request can be made by a CCU to all CPU's simultaneously. If the channel masks are applied differently by the different CPU's, different CI requests could be made, e.g. a different CI request to each CPU, and each such CPU could simultaneously send an interrupt response signal to the CCU.
However, in the latter case, only one of simultaneous CPU response signals could be selected by the CCU, because the On-line CPU Priority Logic would select only one CPU at any one time. Each other CPU channel interrupt response remained pending while the CCU selected them, one at a time, in accordance with the On-line CPU priority logic.
When the On-line logic selects a CPU, the unselected CPUs are not released for handling another CI until the selected CPU is released when it has received the CSW information. Then all CPU responses then existing contend for priority in the CCU, which then determines which CPU will next handle a CI. Hence, no overlap in CSW generation is obtainable among the CPUs. Thus, the system is arranged for the CCU to control plural simultaneous CIs to be serially handled by the plural CPU's.
After taking the interrupt by storing the CSW and OLD PSW and by accessing the NEW I/O PSW, the interrupted CPU executes the operating system CI handling program. The software may control an interrupted processor to take one or more other interrupts and enqueue them before completing the handling of an interrupt, i.e., nesting the interrupt handling.
In a U.S. Pat. No. 3,421,150 to Quosig et. al. IR's (I/O Interrupt Requests) are queued onto a plurality of lists in main storage. Each IR is put on a list in Main Storage independently of processor selection for handling the IR. Quosig associates the IR lists with different I/O controllers. Quosig sequentially polls his processors in a predetermined priority sequence for determining their interruptability states and selects the first sensed interruptable processor to handle a priority selected IR. Quosig selects the processor in the most interruptable state during the sequential scan.
An article published in the Dec. 1966 Proceedings of the IEEE on pages 1812 to 1819 by R. J. Gountanis and N. L. Viss is similar in subject matter to the disclosure in U.S. Pat. No. 3,421,150.
In a U.S. Pat. No. 4,015,243 to Kurpanek et. al. the queuing of each IR is dependent on prior selection of a processor to handle the IR. To sense processor interrupt states, Kurpanek goes to his processors, while Quosig senses processor line signals sent to his multiprocessor interrupt directory hardware.
On the other hand, the M67-2 MP broadcasts one priority selected IR to all processors in the system. In the M67MP, the processors each determine their acceptance of a broadcast IR, and then the CCU selects an accepting processor and signals the selection to the selected processor. The M67MP processor acceptance signal is "CPU-X Response" to the CCU.
Kurpanek and Quosig have the interrupt control unit select a candidate processor, and then have that processor (rather than the interrupt control unit) determine the acceptance or rejection of the candidate selection.